The correspondance requires some math and is recorded as table in this excel file. Please check that the VME ID register value read back by the script (look for barcode in its output) is the correct one for the actual RC bar code. Example: RC with bar code 3101110095 -  VME ID register is A0.

> more /afs/hep.wisc.edu/cms/RCTlog/daffodil/RC_[today's date].log

This annotated version of the script output gives directions what to look for in detail.

Running the script takes about 2 minutes. The red LED at the front of the RC stays one while the test is running.

This annotated version of the script output gives directions what to look for in detail.

In the case of failure, write into the elog where the program failed, for example " Checking Phase 1 and 3 to Adder 0, Route OP 2 pin 7", if that were the program's last words on the screen before failing.

Before the test patterns are written to the memories (LUTs), the content of each memory addresses is set to zero first. This takes about 0.5 minutes per RC. The red LED on the front of an RC is on while writing to its memories takes place.

Attention: Do connect with a cable ONLY those two cards the script in question specifies. Take all other cables off, they can interfer with the test results in unexpected and undesirable ways.

These chips are located on the top side of the EIC board, the red squares here give you a hint where. The chips are PLCC, with 28 pins. Pin 1 is marked by a little dot over it on the chip plastic case, and the pin numbers increase counter-clock-wise, i.e. the pins at the corners are: Pins 4 & 5, 11 & 12, 18 & 19, 25 & 26.

On the scope, trigger threshold should be about -1.3 V, trigger on the rising edge, use "auto" trigger mode, time axis scale 10 ns, y axis scale 500 mV. The signals are 160 MHz ECL signals, i.e. one bit is 6.25 ns long. Connect the scope probe ground to any of the metal ground pins on the RC.

This checklist and the annotated version of the output of the scripts give directions which pins to check and which values to expect.

The instructions on the checklist concerning running specific vmedia scripts are carried out automatically by the tun_RC_test5n scripts. You do not have to carry them out yourself.

Before the test patterns are written to the memories (LUTs), the content of each memory addresses is set to zero first. This takes about 0.5 minutes per RC. The red LED on the front of an RC is on while writing to its memories takes place.

These chips are located on the top side of the EIC board, the red squares here give you a hint where. The chips are PLCC, with 28 pins. Pin 1 is marked by a little dot over it on the chip plastic case, and the pin numbers increase counter-clock-wise, i.e. the pins at the corners are: Pins 4 & 5, 11 & 12, 18 & 19, 25 & 26.

On the scope, trigger threshold should be about -1.3 V, trigger on the rising edge, use "auto" trigger mode, time axis scale 10 ns, y axis scale 500 mV. The signals are 160 MHz ECL signals, i.e. one bit is 6.25 ns long. Connect the scope probe ground to any of the metal ground pins on the RC.

This checklist and the annotated version of the output of the scripts give directions which pins to check and which values to expect.
The instructions on the checklist concerning running specific vmedia scripts are carried out automatically by the tun_RC_test6n scripts. You do not have to carry them out yourself.

Attention: You have to probe on the JSC connectors J4, J5, J6, NOT on the corresponding connectors on the JSC Mezzanine card.

The pin numbering of J4, J5, J6 is here. Attention: Pin 34 on J4, J5, J6 on the JSC is in the LOWER LEFT CORNER.

Attention: When the RC to be tested is in slot 3, as it should, you have to check only  those pins on the JSC output connectors that correspond to  RC slot3, i.e. J6 pins 13 - 29 and pins 59 - 63.

On the scope, thrigger threshold should be about -1.3 V, trigger on the rising edge, time axis scale 50 ns, y axis scale 500 mV. The signals are 80 MHz ECL signals, i.e. one bit is 12.5 ns long.

Use pin 35 on J6 as trigger source. The bit pattern on this pin is 0001 (hex) = 00000000000001, i.e. only a single bit should be set to "1". It is pratical to use a thin wire to connect the scope probe to the trigger pin. For this, use the scope probe with one of the cylindrical hoods with a hook at their tip. Use the connector metal shell as the scope probe ground.

Look at the other pins with the second scope probe. The table below lists what you should see on the scope. The bottom signal on the scope shots is always one of the trigger bits.
Note: The direction of the time axis on the scope is from left to right and the LSB comes first in time, i.e. the LSB is in the leftmost position. When writing/reading a binary number on paper, the direction is also from left to right, but with the LSB on the rightmost position.

Attention: You have to rpobe on the JSC Mezzanine card connectors J5, J6, NOT the J5, J6 connectors directly on the JSC.

The pin numbering of J5 and J6 is here. Attention: Pin 34 on J5, J6 on the JSC Mezzanine card is in the UPPER RIGHT CORNER.

On the scope, thrigger threshold should be about -1.3 V, trigger on the rising edge, time axis scale 50 ns, y axis scale 500 mV. The signals are 80 MHz ECL signals, i.e. one bit is 12.5 ns long.

Use either pin 27 or pin 29 as trigger source. The bit pattern on these pins is 0002 (hex) = 00000000000010, i.e. only a single bit should be set to "1". It is pratical to use a thin wire to connect the scope probe to the trigger pin. For this, use the scope probe with one of the cylindrical hoods with a hook at their tip. Use the connector metal shell as the scope probe ground.

Look at the other pins with the second scope probe. The table below lists what you should see on the scope. The bottom signal on the scope shots is always one of the trigger bits.
Note: The direction of the time axis on the scope is from left to right and the LSB comes first in time, i.e. the LSB is in the leftmost position. When writing/reading a binary number on paper, the direction is also from left to right, but with the LSB on the rightmost position.

This annotated version of the script output give some more directions.
Before the test patterns are written to the memories (LUTs), the content of each memory addresses is set to zero first. For the RCs, this takes a while. The red LED on the front of the cards are on while writing to the memories takes place.

With SW 16.1 on, this results in the data on the first clock cycle being zeroed as result of the non-zero EDC (error detection code).
This is visible in the Data0 - Data15 patterns. To see them on the scope, thrigger threshold should be about -1.3 V, time axis scale 100 ns, y axis scale 500 mV. The signals are 80 MHz ECL signals, i.e. one bit is 12.5 ns long.  Trigger on the EDC of the phase ASIC in question. The data bits should be zero on the clock cycle that coincides with the EDC being "1".